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In the circuit shown below, assume that the comparators are ideal and all components have zero propagation delay. In one period of the input signal $V_{in}=6 \sin(\omega t)$, the fraction of the time for which the output $OUT$ is in logic state $HIGH$ is 

  1. $1/12$
  2. $1/2$
  3. $2/3$
  4. $5/6$
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