In the figure shown, the positive edge triggered $\mathrm{D}$ flip-flops are initially reset to $Q=0$. The logic gates and the multiplexers have no propagation delay. After reset, a train of clock pulses (CLK) are applied. The logic-states of the inputs DIN, $\mathrm{S}$ and the clock pulses are also shown in the figure. Assuming no timing violations, the sequence of output $\mathrm{Y}$ from the $3^{\text {rd }}$ clock to the $5^{\text {th }}$ clock, $\mathrm{Y}_{3} \mathrm{Y}_{4} \mathrm{Y}_{5}$ is
$001$
$010$
$000$
$011$