In the circuit shown below, $\text{Q}_1$ has negligible collector-to-emitter saturation voltage and the diode drops negligible voltage across it under forward bias. If $\text{V}_{cc}$ is $+5\;\text{V, X and Y}$ are digital signals with $0\;\text{V}$ as logic $0$ and $\text{V}_{cc}$ as logic $1$, then the Boolean expression for $\text{Z}$ is
- $\text{XY}$
- $\overline{X}\text{Y}$
- $\text{X}\overline{Y}$
- $\overline{XY}$