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Recent questions tagged latch
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GATE2017: 43
The two inputs $A$ and $B$ are connected to an $R-S$ latch via two $AND$ gates as shown in the figure. If $A=1$ and $B=0$, the output $Q\overline{Q}$ is $00$ $10$ $01$ $11$
The two inputs $A$ and $B$ are connected to an $R-S$ latch via two $AND$ gates as shown in the figure. If $A=1$ and $B=0$, the output $Q\overline{Q}$ is$00$$10$$01$$11$
soujanyareddy13
2.7k
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soujanyareddy13
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Nov 2, 2020
Digital Electronics
gate2017-in
digital-electronics
sequential-circuit
latch
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GATE2015-24
In the circuit shown, the switch is momentarily closed and then opened. Assuming the logic gates to have equal non-zero delay, at steady state, the logic states of X and Y are $X$ is latched, $Y$ toggles continuously $X$ and $Y$ are both latched $Y$ is latched, $X$ toggles continuously $X$ and $Y$ both toggle continuously
In the circuit shown, the switch is momentarily closed and then opened. Assuming the logic gates to have equal non-zero delay, at steady state, the logic states of X and ...
Milicevic3306
7.9k
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Milicevic3306
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Mar 26, 2018
Digital Electronics
gate2015-in
digital-electronics
sequential-circuit
latch
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