Recent questions tagged sequential-circuit / GO Instrumentation

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GATE IN 2021 | Question: 32
A $10$ $^1/_2$ digit Counter-timer is set in the 'frequency mode' of operation (with $T_{s}=1 s$). For a specific input, the reading obtained is $1000$. Without disconnecting this input, the Counter-timer is changed to operate in the 'Period mode' and the range selected is microseconds ($\mu s$, with $f_{s} = 1\text{ MHz}$). The counter will then display $0$ $10$ $100$ $1000$

A $10$ $^1/_2$ digit Counter-timer is set in the 'frequency mode' of operation (with $T_{s}=1 s$). For a specific input, the reading obtained is $1000$. Without disconnec...

Arjun

2.9k points

Arjun asked Feb 19, 2021

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GATE IN 2021 | Question: 36
Given below is the diagram of a synchronous sequential circuit with one $\text{J-K}$ flip-flop and one $\text{T}$ flip-flop with their outputs denotes as $\text{A}$ and $\text{B}$ ... $00\rightarrow 10\rightarrow 01\rightarrow 11\rightarrow 00 \cdots$ $00\rightarrow 10\rightarrow 11\rightarrow 01\rightarrow 00 \cdots$ $00\rightarrow 01\rightarrow 11\rightarrow 00 \cdots$

Given below is the diagram of a synchronous sequential circuit with one $\text{J-K}$ flip-flop and one $\text{T}$ flip-flop with their outputs denotes as $\text{A}$ and $...

Arjun

2.9k points

Arjun asked Feb 19, 2021

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3

GATE2020 IN: 40
Two flip-flops are interconnected as shown in the figure. The present state of the flip flops are: $A=1, B=1$. The input x is given as $1,0,1$ in the next three clock cycles. The decimal equivalent of $(ABy)_2$ with A beign the $MSB$ and y being the $LSB$, after the 3rd clock cycle is ___________

Two flip-flops are interconnected as shown in the figure. The present state of the flip flops are: $A=1, B=1$. The input x is given as $1,0,1$ in the next three clock cyc...

soujanyareddy13

2.7k points

soujanyareddy13 asked Nov 3, 2020

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4

GATE2020 IN: 43
A $6\frac{1}{2}$ digit timer-counter is set in the ‘time period’ mode of operation and the range is set as ‘ns’. For an input signal, the timer-counter displays $1000000$. With the same input signal, the timer-counter is changed to ‘frequency’ mode of operation and the range is set as ‘Hz’. the display will show the number _______.

A $6\frac{1}{2}$ digit timer-counter is set in the ‘time period’ mode of operation and the range is set as ‘ns’. For an input signal, the timer-counter displays $...

soujanyareddy13

2.7k points

soujanyareddy13 asked Nov 3, 2020

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5

GATE2017: 43
The two inputs $A$ and $B$ are connected to an $R-S$ latch via two $AND$ gates as shown in the figure. If $A=1$ and $B=0$, the output $Q\overline{Q}$ is $00$ $10$ $01$ $11$

The two inputs $A$ and $B$ are connected to an $R-S$ latch via two $AND$ gates as shown in the figure. If $A=1$ and $B=0$, the output $Q\overline{Q}$ is$00$$10$$01$$11$

soujanyareddy13

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soujanyareddy13 asked Nov 2, 2020

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6

GATE2019 IN: 12
The circuit shown in the figure below uses ideal positive edge-triggered synchronous J-K flip flops with outputs X and Y. If the initial state of the output is X =0 and Y =0 just before the arrival of the first clock pulse, the state of the output just before the arrival of the second clock pulse is X=0, Y=0 X=0, Y=1 X=1, Y=0 X=1, Y=1

The circuit shown in the figure below uses ideal positive edge-triggered synchronous J-K flip flops with outputs X and Y. If the initial state of the output is X =0 and Y...

Arjun

2.9k points

Arjun asked Feb 10, 2019

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7

GATE2016-45
A synchronous counter using two J-K flip flops that goes through the sequence of states: $Q_1Q_2=00\rightarrow10\rightarrow01\rightarrow11\rightarrow00 \dots$ is required. To achive this, the inputs to the flip flops are $J_1=Q_2,\;\;\;K_1=0\;\;\;\;;\;J_2={Q_1}’, \;\;K_2=Q_1$ $J_1=1,\;\;\;\;\;K_1=1\;\;\;\;\;;\;J_2={Q_1}, \;K_2=Q_1$ $J_1=Q_2,\;\;K_1={Q_2}’\;;\;J_2=1, \;\;\;\;K_2=1$ $J_1={Q_2}’,\;K_1=Q_2\;\;;\;J_2={Q_1}, \;K_2={Q_1}’$

A synchronous counter using two J-K flip flops that goes through the sequence of states: $Q_1Q_2=00\rightarrow10\rightarrow01\rightarrow11\rightarrow00 \dots$ is required...

Milicevic3306

7.9k points

Milicevic3306 asked Mar 26, 2018

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GATE2015-24
In the circuit shown, the switch is momentarily closed and then opened. Assuming the logic gates to have equal non-zero delay, at steady state, the logic states of X and Y are $X$ is latched, $Y$ toggles continuously $X$ and $Y$ are both latched $Y$ is latched, $X$ toggles continuously $X$ and $Y$ both toggle continuously

In the circuit shown, the switch is momentarily closed and then opened. Assuming the logic gates to have equal non-zero delay, at steady state, the logic states of X and ...

Milicevic3306

7.9k points

Milicevic3306 asked Mar 26, 2018

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9

GATE2013-28
The digital circuit shown below uses two negative edge-triggered D-flip-flops. Assuming initial condition of $Q1$ and $Q0$ as zero, the output $Q1Q0$ of this circuit is $\text{00,01,10,11,00 $\dots$}$ $\text{00,01,11,10,00 $\dots$}$ $\text{00,11,10,01,00 $\dots$}$ $\text{00,01,11,11,00 $\dots$}$

The digital circuit shown below uses two negative edge-triggered D-flip-flops. Assuming initial condition of $Q1$ and $Q0$ as zero, the output $Q1Q0$ of this circuit is $...

Milicevic3306

7.9k points

Milicevic3306 asked Mar 25, 2018

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10

GATE2012-14
Consider the given circuit. In the circuit, the race round does not occur occurs when $\text{CLK}=0$ occurs when $\text{CLK}=1$ and $\text{A=B=1}$ occurs when $\text{CLK=1}$ and $\text{A=B=0}$

Consider the given circuit.In the circuit, the race rounddoes not occuroccurs when $\text{CLK}=0$occurs when $\text{CLK}=1$ and $\text{A=B=1}$occurs when $\text{CLK=1}$ a...

Milicevic3306

7.9k points

Milicevic3306 asked Mar 25, 2018

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11

GATE2018IN: 44
A 2-bit synchronous counter using two $J-K$ flip flops is shown. The expressions for the inputs to the $J-K$ flip flops are also shown in the figure. The output sequence of the counter starting from $Q_1Q_2 = 00$ is $00 \rightarrow 11 \rightarrow 10 \rightarrow 01 \rightarrow 00 …$ $00 \rightarrow 01 \rightarrow 10 \rightarrow 11 \rightarrow 00…$ $00 \rightarrow 01 \rightarrow 11 \rightarrow 10 \rightarrow 00…$ $00 \rightarrow 10 \rightarrow 11 \rightarrow 01 \rightarrow 00 ...$

A 2-bit synchronous counter using two $J-K$ flip flops is shown. The expressions for the inputs to the $J-K$ flip flops are also shown in the figure. The output sequence ...

gatecse

1.4k points

gatecse asked Feb 20, 2018