The digital circuit shown below uses two negative edge-triggered D-flip-flops. Assuming initial condition of $Q1$ and $Q0$ as zero, the output $Q1Q0$ of this circuit is
- $\text{00,01,10,11,00 $\dots$}$
- $\text{00,01,11,10,00 $\dots$}$
- $\text{00,11,10,01,00 $\dots$}$
- $\text{00,01,11,11,00 $\dots$}$