Recent questions tagged flip-flops

The initial state of $Q_{3} Q_{2} Q_{1} Q_{0}$ in the digital circuit shown below is $1011$.The new value of $Q_{3} Q_{2} Q_{1} Q_{0}$ after two rising edges of the clock...

​​​​In the figure shown, the positive edge triggered $\mathrm{D}$ flip-flops are initially reset to $Q=0$. The logic gates and the multiplexers have no propagation delay....

Two flip-flops are interconnected as shown in the figure. The present state of the flip flops are: $A=1, B=1$. The input x is given as $1,0,1$ in the next three clock cyc...

Consider the given circuit.In the circuit, the race rounddoes not occuroccurs when $\text{CLK}=0$occurs when $\text{CLK}=1$ and $\text{A=B=1}$occurs when $\text{CLK=1}$ a...