Questions without an upvoted answer in Digital Electronics

The maximum signal to quantization noise ratio (SQNR) for a $16$-bit analog-todigital converter is approximately $\_\_\_\_\_\_$ $\mathrm{dB}$.$48$$68$$88$$98$

The minimum number of comparators required in a $6$-bit flash analog-to-digital converter is $\_\_\_\_\_\_$. (answer in integer)

The initial state of $Q_{3} Q_{2} Q_{1} Q_{0}$ in the digital circuit shown below is $1011$.The new value of $Q_{3} Q_{2} Q_{1} Q_{0}$ after two rising edges of the clock...

Which of the following functions represent(s) the output of the CMOS logic-gate shown in the circuit below?$f=\overline{\mathrm{A}}+\overline{\mathrm{B}} \cdot \overline{...

A $16$ -bit processor has $16$ -bit wide instructions and a few internal registers. Every $16$ -bit instruction is encoded in a fixed format with one operation code of $7...

A digital counter increments its count every $0.1 \mu \mathrm{~s}$. The counter is used in an instrument to measure frequency. The counter is operated for one period of t...

The minimized expression of the Boolean function $\mathrm{Y}(\mathrm{P}, \mathrm{Q}, \mathrm{R})$ implemented by the multiplexer (MUX) circuit shown in the figure is$\mat...

The $4$-bit signed $2$'s complement form of $(5)_{10}+(5)_{10}$ is$(-6)_{10}$$(-7)_{10}$$(-5)_{10}$$(-8)_{10}$

A dual-slope ADC has a fixed integration time of $100 \: \mathrm{ms}$. The reference voltage of the ADC is $-5 \: \mathrm{V}$. The time taken by the ADC to measure an inp...

An $8$-bit microprocessor has $16$ -bit address bus $\left(\mathrm{A}_{15}-\mathrm{A}_{0}\right)$ where $\mathrm{A}_{0}$ is the LSB. As shown in Figure (a), it has a pre-...

A $3$-bit DAC is implemented using ideal opamp and switches as shown in the figure. Each of the switches gets closed when its corresponding digital input is at logic $1$....

Among the given options, the simplified form of the Boolean function $\mathrm{F=(A+\bar{A} \cdot B)+\bar{A} \cdot(A+\bar{B}) \cdot C}$ is$\mathrm{A+B+C}$$\mathrm{A \cdot ...

​​​​In the figure shown, the positive edge triggered $\mathrm{D}$ flip-flops are initially reset to $Q=0$. The logic gates and the multiplexers have no propagation delay....

The $4$-point DFTs of two sequences $x[n]$ and $y[n]$ are $X[k]=[1,-j, 1, j]$ and $Y[k]=[1,3 j, 1,-3 j]$, respectively. Assuming $z[n]$ represents the $4$ -point circular...

An ADC has a full scale voltage of $1.4 \mathrm{~V}$, resolution of $200 ~\mathrm{mV}$, and produces binary output data. The input signal of the ADC has a bandwidth of $5...

The table shows the present state $\mathrm{Q}(\mathrm{t})$, next state $\mathrm{Q}(\mathrm{t}+1)$, and the control input in a flip-flop. Identify the flip-flop.$$\begin{a...

Match the Exclusive-$\text{OR (XOR)}$ operations $\text{(i)}$ to $\text{(iv)}$ with the results $\text{(p)}$ to $\text{(s),}$ where $X$ is a Boolean input.$$\begin{array}...

Choose the fastest logic family among the following: Transistor-Transistor Logic Emitter-Coupled Logic CMOS LogicResistor-Transistor Logic

The simplified form of the Boolean function $\mathrm{F}(W, X, Y, Z)=\Sigma(4,5,10,11,12,13$, $14,15)$ with the minimum number of terms and smallest number of literals in ...

For the given digital circuit, $\mathrm{A}=\mathrm{B}=1$. Assume that $\mathrm{AND}, \mathrm{OR}$, and $\text{NOT}$ gates have propagation delays of $10 \mathrm{~ns}, 10 ...

In the circuit shown, the initial binary content of shift register $A$ is $1101$ and that of shift register $B$ is $1010.$ The shift registers are positive-edge triggered...

The logic block shown has an output $F$ given by ________$A + B$$A \cdot \overline{B}$$A + \overline{B}$$\overline{B}$

An analog-to-digital converter with resolution $0.01 \; \text{V}$ converts analog signals between $0 \; \text{V}$ to $+10 \; \text{V}$ to an unsigned binary output. The m...

Consider $24$ voice signals being transmitted without latency using time-division multiplexing. If each signal is sampled at $12 \; \text{kHz}$ and represented by an $8$-...

A resistor ladder digital-to-analog converter $\text{(DAC)}$ receives a digital input that results in the circuit having the state as shown in the figure. For this digita...

The digital circuit shown ________is a divide-by-$5$ counteris a divide-by-$7$ counteris a divide-by-$8$ counterdoes not function as a counter due to disjoint cycles of s...

$A= a_{1}a_{0}$ and $B= b_{1}b_{0}$ are two $2$–bit unsigned binary numbers. If $F(a_{1},a_{0},b_{1},b_{0})$ is a Boolean function such that $F=1$ only when $A>B,$ and $F...

In the circuit shown, the switch is initially closed. It is opened at $t=0 \; \text{s}$ and remains open thereafter. The time (in milliseconds) at which the output voltag...

For a $4$-bit Flash type Analog to Digital Convertor $\text{(ADC)}$ with full scale input voltage range $\text{"V"}$ which of the following statement$\text{(s)}$ is/are t...

A $16$-bit microprocessor has twenty address lines ($A_{0}$ to $A_{19}$) and $16$ data lines. The higher eight significant lines of the data bus of the processor are tied...

Boolean function $\text{F}$ of three variable $\text{X, Y,}$ and $\text{Z}$ is given as$F\left ( X, Y, Z \right )=\left ( {X}' + Y + Z \right )\cdot \left ( X + {Y}' + {Z...

A $10$ $^1/_2$ digit Counter-timer is set in the 'frequency mode' of operation (with $T_{s}=1 s$). For a specific input, the reading obtained is $1000$. Without disconnec...

Given below is the diagram of a synchronous sequential circuit with one $\text{J-K}$ flip-flop and one $\text{T}$ flip-flop with their outputs denotes as $\text{A}$ and $...

The input signal shown belowis passed through the filter with the following tapsThe number of non-zero output samples is ________________.

A signal having a bandwidth of $\text{5 MHz}$ is transmitted using the Pulse code modulation $\text{(PCM)}$ scheme as follows. The signal is sampled at a rate of $50\%$ a...

A $\text{200 mV}$ full-scale dual-slope analog to digital converter $\text{(DS-ADC)}$ has a reference voltage of $\text{100 mV}$. The first integration time is set as $\t...