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Recent activity in Digital Electronics

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GATE IN 2022 | Question: 13
The output $\text{F}$ of the digital circuit shown can be written in the form(s) __________$\overline{A \cdot B}$$\overline{A} + \overline{B}$$\overline{A+B}$$\overline{A...
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GATE IN 2025 | Question: 30
The clock frequency of the digital circuit shown in the figure is $12 \: \mathrm{MHz}$. The frequencies of the output $(\mathrm{F})$ corresponding to Control $=0$ and Con...
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GATE IN 2026 | Question: 52
A digital counter increments its count every $0.1 \mu \mathrm{~s}$. The counter is used in an instrument to measure frequency. The counter is operated for one period of t...
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GATE IN 2026 | Question: 46
A $16$ -bit processor has $16$ -bit wide instructions and a few internal registers. Every $16$ -bit instruction is encoded in a fixed format with one operation code of $7...
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GATE IN 2026 | Question: 45
Which of the following functions represent(s) the output of the CMOS logic-gate shown in the circuit below?$f=\overline{\mathrm{A}}+\overline{\mathrm{B}} \cdot \overline{...
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GATE IN 2026 | Question: 37
The initial state of $Q_{3} Q_{2} Q_{1} Q_{0}$ in the digital circuit shown below is $1011$.The new value of $Q_{3} Q_{2} Q_{1} Q_{0}$ after two rising edges of the clock...
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GATE IN 2026 | Question: 25
The minimum number of comparators required in a $6$-bit flash analog-to-digital converter is $\_\_\_\_\_\_$. (answer in integer)
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GATE IN 2026 | Question: 13
The maximum signal to quantization noise ratio (SQNR) for a $16$-bit analog-todigital converter is approximately $\_\_\_\_\_\_$ $\mathrm{dB}$.$48$$68$$88$$98$
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GATE IN 2024 | Question: 48
An ADC has a full scale voltage of $1.4 \mathrm{~V}$, resolution of $200 ~\mathrm{mV}$, and produces binary output data. The input signal of the ADC has a bandwidth of $5...
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GATE IN 2024 | Question: 43
The $4$-point DFTs of two sequences $x[n]$ and $y[n]$ are $X[k]=[1,-j, 1, j]$ and $Y[k]=[1,3 j, 1,-3 j]$, respectively. Assuming $z[n]$ represents the $4$ -point circular...
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GATE IN 2024 | Question: 32
​​​​In the figure shown, the positive edge triggered $\mathrm{D}$ flip-flops are initially reset to $Q=0$. The logic gates and the multiplexers have no propagation delay....
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GATE IN 2025 | Question: 19
A Boolean function $X$ is given as $X=\bar{A} \bar{B}+\bar{A} \bar{C}$. The reduced form of $\bar{X}$ is$\bar{A}+\bar{B}+\bar{C}$$A+B C$$\bar{A}+\bar{B}+C$$B+A C$
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GATE IN 2024 | Question: 6
Among the given options, the simplified form of the Boolean function $\mathrm{F=(A+\bar{A} \cdot B)+\bar{A} \cdot(A+\bar{B}) \cdot C}$ is$\mathrm{A+B+C}$$\mathrm{A \cdot ...
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GATE IN 2025 | Question: 33
A $3$-bit DAC is implemented using ideal opamp and switches as shown in the figure. Each of the switches gets closed when its corresponding digital input is at logic $1$....
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GATE IN 2025 | Question: 32
An $8$-bit microprocessor has $16$ -bit address bus $\left(\mathrm{A}_{15}-\mathrm{A}_{0}\right)$ where $\mathrm{A}_{0}$ is the LSB. As shown in Figure (a), it has a pre-...
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GATE IN 2025 | Question: 24
A dual-slope ADC has a fixed integration time of $100 \: \mathrm{ms}$. The reference voltage of the ADC is $-5 \: \mathrm{V}$. The time taken by the ADC to measure an inp...
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GATE IN 2025 | Question: 8
The $4$-bit signed $2$'s complement form of $(5)_{10}+(5)_{10}$ is$(-6)_{10}$$(-7)_{10}$$(-5)_{10}$$(-8)_{10}$
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GATE IN 2025 | Question: 7
The minimized expression of the Boolean function $\mathrm{Y}(\mathrm{P}, \mathrm{Q}, \mathrm{R})$ implemented by the multiplexer (MUX) circuit shown in the figure is$\mat...
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GATE IN 2022 | Question: 11
The logic block shown has an output $F$ given by ________$A + B$$A \cdot \overline{B}$$A + \overline{B}$$\overline{B}$
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GATE IN 2021 | Question: 10
For a $4$-bit Flash type Analog to Digital Convertor $\text{(ADC)}$ with full scale input voltage range $\text{"V"}$ which of the following statement$\text{(s)}$ is/are t...
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GATE IN 2021 | Question: 44
The input signal shown belowis passed through the filter with the following tapsThe number of non-zero output samples is ________________.
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GATE IN 2021 | Question: 54
A signal having a bandwidth of $\text{5 MHz}$ is transmitted using the Pulse code modulation $\text{(PCM)}$ scheme as follows. The signal is sampled at a rate of $50\%$ a...
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GATE2019 IN: 20
An 8-bit weighted resistor digital-to-analog converter(DAC) has the smallest resistance of 500 $\Omega$. The largest resistance has a value $\_\_\_\_$ k$\Omega$.
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GATE2019 IN: 36
In the circuit below, the light dependent resistor $(LDR)$ receives light from the $LED$. The $LDR$ has resistances of $5\;k\Omega$ and $500\;\Omega$ under dark and illum...
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GATE2019 IN: 43
The frequency response of a digital filter H($\omega$) has the following characteristicsPassband: 0.95$\le$|H($\omega$|$\le$1.05 for 0$\le$$\omega$$\le$0.3$\pi$ andStopba...
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GATE2018IN: 53
The sampling rate for Compact Discs $(CDs)$ is $44,000\; samples/s$. If the samples are quantized to $256$ levels and binary coded, the corresponding bit rate (in bits pe...
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GATE2018IN: 17
For the 3-bit binary counter shown in the figure, the output increments at every positive transition in the clock(CLK). Assume ideal diodes and the starting state of the ...
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GATE2018IN:19
The number of comparators required for implementing an 8-bit flash analog-to-digital converter is8128255256
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GATE IN 2017 | Question: 19
An $8$-bit microcontroller with $16$ address lines has $3$ fixed interrupts i.e., $\text{Int 1}$, $\text{Int 2}$ and $\text{Int 3}$ with corresponding interrupt vector a...
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GATE2016-48
The comparators (output=$’1’$, when input $\underline{>}$ and output=$’0’$, when input$<0$), exclusive-OR gate and the unity gain low-pass filter given in the circuit are...
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GATE2015-22
Consider the logic circuit with input signal $\text{TEST}$ shown in the figure. All gates in the figure shown have identical non-zero delay. The signal $\text{TEST}$ whic...
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GATE2015-51
For the circuit shown in the figure, the rising edge triggered D-flip flop with asynchronous reset has a clock frequency of $\text{1 Hz}$. The $\text{NMOS}$ transistor ha...
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GATE2015-49
An $ADC$ is interfaced with a microprocessor as shown in the figure. All signals have been indicated with typical notations. Acquisition of one new sample of the analog i...
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GATE2014-17
The figure is a logic circuit with inputs $A$ and $B$ and output $Y.V_{95}=+5\;V$. The circuit is of type$NOR$$AND$$OR$$NAND$
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GATE2014-43
The circuit in the figure represents a counter-based unipolar $ADC$. when $SOC$ is asserted the counter is reset and clock is enabled so that the counter counts up and th...
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GATE2014-42
A microprocessor accepts external interrupts (Ext INT) through a Programmable Interrupt Controller as shown in the figure. Assuming vectored interrupt, a correct sequence...
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GATE2014-41
An $N-$bit, $ADC$ has an analog reference voltage $V$. Assuming zero mean and uniform distribution of the quantization error, the quantization noise power will be:$\frac{...
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GATE IN 2013 | Question: 44
In the circuit shown below, $\text{Q}_1$ has negligible collector-to-emitter saturation voltage and the diode drops negligible voltage across it under forward bias. If $\...
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GATE IN 2013 | Question: 19
A bulb in a staircase has two switches, one switch being at the ground floor and the other one at the first floor. The bulb can be turned $ON$ and also can be turned $OFF...
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GATE IN 2012 | Question: 35
The state transition diagram for the logic circuit shown is
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